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1 august 2004 IDT82V2048L octal t1/e1 short haul analog front end idt and the idt logo are trademarks of integrated device technology, inc. dsc-6527/- ? 2004 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. industrial temperature ranges features ? octal t1/e1 short haul analog front end which supports 100 ? ? ? ? ? t1 twisted pair, 120 ? ? ? ? ? e1 twisted pair and 75 ? ? ? ? ? e1 coaxial applications ? built-in transmit pre-equalization meets g.703 & t1.102 ? digital/analog los detector meets itu g.775, ets 300 233 and t1.231 ? itu g.772 non-intrusive monitoring for in-service testing for any one of channel1 to channel7 functional block diagram slicer peak detector line driver waveform shaper los detector one of eight identical channels register file control interface clock generator mode[2:0] cs ts2/sclk/ale/as ts1/rd/r/w ts0/sdi/wr/ds sd0/rdy/ack int d/ad[7:0] mc/a[4:0] mclk trst tck tms tdi tdo jtag tap rtipn rringn ttipn tringn vdd io vddt vddd vdda losn rcn rdpn rdnn tclkn tdnn tdpn g.772 monitor transmit all ones oe clke 6527 drw01 figure - 1. block diagram ? low impedance transmit drivers with high-z ? selectable hardware and parallel/serial host interface ? hitless protection switching (hps) for 1 to 1 protection with- out relays ? jtag boundary scan for board test ? 3.3v supply with 5v tolerant i/o ? low power consumption ? operating t emperature range: -40c to +85c ? available in 144-pin thin quad flat pack (tqfp_144_da) and 160-pin plastic ball grid array (pbga) packages
2 industrial temperature ranges octal t1/e1 short haul analog front end figure - 2a. tqfp package pin assignment pin configurations tdn4 rc4 rdp4 rdn4 los4 oe clke vddt4 ttip4 tring4 gndt4 rtip4 rring4 gndt5 tring5 ttip5 vddt5 rring5 rtip5 vddt6 ttip6 tring6 gndt6 rtip6 rring6 gndt7 tring7 ttip7 vddt7 rring7 rtip7 los7 rdn7 rdp7 rc7 tdn7 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 tdp7 tclk7 los6 rdn6 rdp6 rc6 tdn6 tdp6 tclk6 mclk mode2 a4 mc3/a3 mc2/a2 mc1/a1 mc0/a0 vddio gndio vddd gndd d0/ad0 d1/ad1 d2/ad2 d3/ad3 d4/ad4 d5/ad5 d6/ad6 d7/ad7 tclk1 tdp1 tdn1 rc1 rdp1 rdn1 los1 tclk0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 tdn3 rc3 rdp3 rdn3 los3 rtip3 rring3 vddt3 ttip3 tring3 gndt3 rring2 rtip2 gndt2 tring2 ttip2 vddt2 rtip1 rring1 vddt1 ttip1 tring1 gndt1 rring0 rtip0 gndt0 tring0 ttip0 vddt0 mode1 los0 rdn0 rdp0 rc0 tdn0 tdp0 td4 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ? idt 82v2048l da 6527 drw02 tclk4 los5 rdn5 rdp5 rc5 tdn5 tdp5 tclk5 tdi tdo tck tms trst ic ic vddio gndio vdda gnda mode0 cs ts2/sclk/ale/ as ts1/ rd /r/ w ts0/sdi/ wr / ds sdo/rdy/ ack int tclk2 tdp2 tdn2 rc2 rdp2 rdn2 los2 tclk3 tdp3
3 industrial temperature ranges octal t1/e1 short haul analog front end pin configurations (continued) figure - 2b. pbga160 package pin assignment vddt4 tring4 gndt4 rtip4 rtip7 gndt7 tring7 vddt7 rc4 rdp4 rdn4 rdp7 rc7 vddt5 tring5 gndt5 rtip5 rtip6 gndt6 vddt6 rdn6 rc5 rdp5 rdn5 rdp6 vddt5 ttip5 gndt5 rring5 rring6 gndt6 ttip6 vddt6 tdn6 tclk5 tdp5 tdn5 tdp6 tclk6 los4 los7 los6 oe clke los5 mode2 mclk tms a4 mc3 tdo tdi mc2 mc1 gndio gndio mc0 vddio ic trst d0 vddio gnda gndd d1 vdda ic mode0 d2 vddd cs d3 d4 ts0 ts1 ts2 d5 d6 los3 los0 los1 sdo int los2 mode1 vddt2 ttip2 gndt2 rring2 rring1 gndt1 ttip1 vddt1 tdn1 tclk2 tdp2 tdn2 tdp1 tclk1 vddt2 tring2 gndt2 rtip2 rtip1 gndt1 tring1 vddt1 rdn1 rc2 rdp2 rdn2 rdp1 rc1 vddt3 ttip3 gndt3 rring0 gndt0 ttip0 vddt0 tdn0 tclk3 tdp3 tdn3 tdp0 tclk0 vddt3 tring3 gndt3 rtip3 rtip0 gndt0 tring0 vddt0 rdn0 rc3 rdp3 rdn3 rdp0 rc0 vddt7 ttip7 gndt7 rring7 rring4 gndt4 ttip4 vddt4 tdn4 tclk7 tdp7 tdp4 tclk4 tring6 idt 82v2048bb (bottom view) rring3 a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rdn7 tdn7 6527 drw03 rc6 d7 tck
4 industrial temperature ranges octal t1/e1 short haul analog front end pin description: name type pin no description qfp144 bga160 ttip0 45 n5 ttipn/tringn: transmit bipolar tip/ring for channel 0-7 ttip1 52 l5 these pins are the differential line driver outputs. they will be in high impedance state if pin ttip2 57 l10 oe is low or the corresponding pin tclkn is low (pin oe is globe control, while pin tclkn ttip3 64 n10 is per-channel control). in host mode, each pin can be in high impedance state by programming ttip4 117 b10 a ?1? to the corresponding bit in register oe 1 . ttip5 124 d10 ttip6 129 d5 ttip7 analog 136 b5 output tring0 46 p5 tring1 51 m5 tring2 58 m10 tring3 63 p10 tring4 118 a10 tring5 123 c10 tring6 130 c5 tring7 135 a5 rtip0 48 p7 rtipn/rringn: receive bipolar tip/ring for channel 0-7 rtip1 55 m7 these pins are the differential line receiver inputs. rtip2 60 m8 rtip3 67 p8 rtip4 120 a8 rtip5 127 c8 rtip6 132 c7 rtip7 analog 139 a7 input rring0 49 n7 rring1 54 l7 rring2 61 l8 rring3 66 n8 rring4 121 b8 rring5 126 d8 rring6 133 d7 rring7 138 b7 transmit and receive line interface 1 register name is indicated by bold capital letters. oe : output enable register.
5 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 tdp0 37 n2 tdpn/tdn: positive/negative transmit data for channel 0-7 tdp1 30 l2 the nrz data to be transmitted for positive /negative pulse is input on this pin. data on tdpn/ tdp2 80 l13 tdnn are active high and sampled on failling tdp3 73 n13 edge of tclkn. tdp4 108 b13 tdp5 101 d13 tdp6 8 d2 tdp7 i 1 b2 tdn0 38 n3 tdn1 31 l3 tdn2 79 l12 tdn3 72 n12 tdn4 109 b12 tdn5 102 d12 tdn6 7 d3 tdn7 144 b3 tclk0 i 36 n1 tclkn: transmit clock for channel 0-7 tclk1 29 l1 the clock of 1.544mhz (for t1 mode) or 2.048 mhz (for e1 mode) for transmit is input on this tclk2 81 l14 pin. the transmit data at tdpn or tdnn is sampled into the device on falling edge of tclkn. tclk3 74 n14 different combinations of tclkn and mclk result in different modes. it is summarized in tclk4 107 b14 section in table 1 - system interface configuration. tclk5 100 d14 tclk6 9 d1 tclk7 2 b1 tdpn tdnn output pulse 0 0 space 0 1 negative pulse 1 0 postivie pulse 1 1 space
6 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 rdp0 o 40 p2 rdpn/rdn: positive/negative receive data for channel 0-7 rdp1 33 m2 these pins output the raw rz sliced data. the active polarity of rdpn/rdnn is determined rdp2 high-z 77 m13 by pin clke. when pin clk is low, rdpn/rdnn is active low. when pin clke is high, rdp3 70 p13 rpdn/rdnn is active high. rdpn/rdnn will remain active during los. rdpn/rdnn is set rdp4 111 a13 into high impedance when the corresponding receiver is power down. rdp5 104 c13 rdp6 5 c2 rdp7 142 a2 rdn0 41 p3 rdn1 34 m3 rdn2 76 m12 rdn3 69 p12 rdn4 112 a12 rdn5 105 c12 rdn6 4 c3 rdn7 141 a3 rc0 o 39 p1 rcn: recieve pulse for channel 0-7 rc1 32 m1 in data recovery mode, rcn is the output of an internal exclusive or (xor) which is connected rc2 high-z 78 m14 with rdpn and rdnn. the clock is recovered from the signal on rcn externally. if receiver rc3 71 p14 n is power down, the corresponding rcn is in high impedance. rc4 110 a14 rc5 103 c14 rc6 6 c1 rc7 143 a1 mclk i 10 e1 mclk: master clock this is the idependent, free running reference dock. a clock of 1.544 mhz (for t1 mode) or 2.048 mhz (for e1 mode) is supplied to this pin as the clock reference of the device for normal operation. when mclk is low, all the receivers are power down, and the output pins rcn, rdpn, and rdnn are switched to high impedance. in transmit path, the operation mode is decided by the combination of mclk and tclkn (it is summarized in table 1 - system interface configuration). note that wait state generation via rdy/ ack is not available if mclk is not provided. los0 o 42 k4 losn: loss of signal output for channel 0-7 los1 35 k3 a high level on this pin indicates the loss of signal when there is not transition over a specific los2 75 k12 period of time and not enough ones desity in the received signal. the transition will return los3 68 k11 to low automatically when there is enough transition over a specific period of time with a certain los4 113 e11 ones desity in the received signal. the los assertion and desertion criteria are described los5 106 e12 in the functional description. los6 3 e13 los7 140 e4
7 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 mode2 i 11 e2 mode2: control mode select 2 (1) this signal on this pin determines which control mode is selected to control the device: (pulled to vddio / 2) hardware control pins include mode[2:0], ts[2:0], clke and oe. serial host interface pins include cs, sclk, sdi, sdo, and int and parallel host interface pins include cs, a[4:0], d[7:0], wr/ds, rd/rw, ale/as, int and rdy/ack. the device supports multiple parallel host interace as follows (refer to mode1 and mode0 pin description below for details): mode1 i 43 k2 mode1: control mode select 1 (1) in parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is low, and operates with multiplexed address and data bus when this pin is high. in serial host mode or hardware mode, this pin should be grounded. mode0 i 88 h12 mode0: control mode select (1) in host mode, the parallel host interface is configured for motorola compatible hosts when this pin is low, or for intel compatible hosts when this pin is high. in serial host mode or hardware mode, this pin should be grounded. cs i 87 j11 cs : chip select (active low) in host mode, this pin is asserted low by the host to enable host interface. a transition from (pulled to high to low must occur on this pin for each read/write operation and the level must not return vddio / 2) to high until the operation is over. in hardware control mode, this pin should be pulled to vddio/2. hardware/host control mode mode 2 control interface low control by hardware mode vddio/2 control by serial host interface high control by parallel host interface mode [2:0] host interface 100 non-multiplexed motorola mode interface 101 non-multiplexed intel mode interface 110 multiplexed motorola mode interface 111 multiplexed intel mode interface note : 1. in host mode operation, extended register e-afe has to be set to ff h for proper device operation. see extended register description for details.
8 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 ts2/ i 86 j12 ts2: template select 2 sclk/ in hardware control mode, the signal on this pin is the most significant bit for the transmit template ale/ as select. refer to transmit template of the functional description for details. sclk: shift clock in serial host mode, the signal on this pin is the shift clock for the serial interface. data on pin sdo is clocked out on falling edges of sclk if pin clke is low, or on rising edge of sclk if pin clke is high. data on pin sdi is always sampled on rising edges of sclk. ale: address latch enable in parallel intel multiplexed host mode, the address on ad[4:0] is sampled into the device on falling edges of ale (signals on ad[7:5] are ignored). in non-multiplexed host mode, ale should be pulled high. as : address strobe (active low) in parallel motorola multiplexed host mode, the address on ad[4:0] is latched into the device on fallind edges of as (signals on ad[7:5] are ignored). in non-multiplexed host mode, as should be pulled high. ts1/ rd / i 85 j13 ts1: template select 1 r/ w in hardware control mode, the signal on this pin is the second most significant bit for the transmit template select. refer to transmit template of functional description for details. rd : read strobe (active low) in parallel intel multiplexed or non-multiplexed host mode, this pin is active for read operation. r/ w : read/write select in parallel motorola multiplexed host mode, the pin is active low for write operation and high for read operation. ts0/ i 84 j14 ts0: template select 0 sdi/ wr / in hardware control mode, the signal on this pin is the least significant bit for the transmit template ds select. refer to transmit template of functional description for detail. sdi: serial data input in serial host mode, this pin input the data to the serial interface. data on this pin is sampled on rising edges of sclk. wr : write strobe (active low) in parallel intel host mode, this pin is is active low during write operation. the data on d[7:0] (in non-multiplexed mode) or a[7:0] (in multiplexed mode) is sampled into the device on rising edges of wr . ds : data strobe (active low) in parallel motorola host mode, this pin is active low. during a write operation (r/ w = 0), the data on d[7:0] (in non-multiplexed mode) or ad[7:0] (in multiplexed mode) is sampled into the device on rising edges of ds . during a read operatoin (r/ w = 1), the data is driven to d[7:0] (in non-multipled mode) or ad[7:0} (in multiplexed mode) by the device on rising edges of ds . in parallel motorola non-multiplexed host mode, the address information on the 5 bits of address bus a[4:0] are latched into the device on the falling edge of ds .
9 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 sdo/ o 83 k14 sdo: serial data output rdy/ in serial host mode, the data is output on this pin. in serial write operation , sdo is always ack in high impedance. in serial read operation, sdo is in high impedance only when sdi is in address/command byte. data on pin sdo is clocked out of the device on falling edges of sclk in pin clke is low, or on rising edges of sclk if pin clke is high. rdy: ready output in parallel intel host mode, the high level of this pin reports to the host that bus cycle can be completed, while low reports the host must insert wait status. ack : acknowledge output (active low) in parallel motorola host mode, the low level of this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. int o 82 k13 int : interrupt (active low) open this in the open drain, active low interrupt output. four sources may cause the interrupt (refer drain to interrupt handling of functional description for details). d7/ad7 i/o 28 k1 dn: data bus 7-0 d6/ad6 27 j1 in non-multiplexed host mode, these pins are the bi-directional data bus. d5/ad5 26 j2 d4/ad4 high-z 25 j3 adn: address/data bus 7-0 d3/ad3 24 j4 in multiplexed host mode, these pins are in multiplexed bi-directional address/data bus. d2/ad2 23 h2 d1/ad1 22 h3 in hardware mode, these pins should be tied to vddio/2. in serial host mode, these pins should d0/ad0 21 g2 be grounded.
10 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 a4 i 12 f4 mcn: performance monitor configuration 4-0 mc3/a3 13 f3 in hardware control mode, a4 must be connected to gnd, mc[3:0] are used to select one mc2/a2 14 f2 transmitter or receiver of the channel 1 to 7 for non-intrusive monitoring. channel 0 is used mc1/a1 15 f1 as the monitoring channel. if a transmitter is monitored, signals on the corresponding pins mc0/a0 16 g3 ttipn and tringn are internally transmitted to rtipn and rringn are internally transmitted to rtip0 and rring0. the clock and data recovery circuit in receiver 0 can then output the monitored clock pin rc0 as well as the monitored data to rdp0 and rdn0 pins. the signals monitored by channel 0 can be routed to ttip0/ring0 by activating the remote loopback in this channel. performance monitor configuration determines by mc[3:] is shown below. note that if mc[2:0] = 000, the device is in normal operation of all the channels. an: address bus 4-0 when pin mode1 is low, the parallel host interface operates with separate address and data bus. in this mode, the signal on this pin is the address bus of the host interface. oe i 114 e14 oe: output driver enable pulling this pin to low can make all driver output into high impedance state immediately for redundacy application without external mechanical relays. in this condition, all the other internal circuits remain active. clke i 115 e113 clke: clock edge select the signal on this pin determines the active edge of rcn, rdpn, rdnn and sclk (refer to functional description and table 2 ). mc[3:] monitoring configuration 0000 normal operation without monitoring 0001 monitoring receiver 1 0010 monitoring receiver 2 0011 monitoring receiver 3 0100 monitoring receiver 4 0101 monitoring receiver 5 0110 monitoring receiver 6 0111 monitoring receiver 7 1000 normal operation without monitoring 1001 monitoring transmitter 1 1010 monitoring transmitter 2 1011 monitoring transmitter 3 1100 monitoring transmitter 4 1101 monitoring transmitter 5 1110 monitoring transmitter 6 1111 montioring transmitter 7
11 industrial temperature ranges octal t1/e1 short haul analog front end pin description (continued): name type pin no description qfp144 bga160 trst i 95 g12 trst : jtag test port reset (active low) this is the active low asynchronous reset to the jtag test port. this pin has an internal pullup pullup resistor and it can be left disconnected. tms i 96 f11 tms: jtag test mode select this signal on this pin controls the jtag test performance and is clocked into the device on pullup rising edges of tck. this pin has an internal pullup resister and it can be left disconnected. tck i 97 f14 tck: jtag test clock this pin input the clock of the jtag test. the data on tdi and tms are clocked into the device on rising edges of tck. tdo is a high-z output signal. it is active only when scanning of high-z data is out. tdi i 99 f12 tdi: jtag test data input this pin input the serial data of the jtag test. the data on the tdi is clocked into the device pullup on rising edges of tck. this pin has an internal pullup and it can be left disconnected. ic - 93 g13 ic: internal connected (leave it open for normal operation). ic - 94 h13 ic: internal connected (leave it open for normal operation). supplies and grounds vddio - 17 g1 3.3v i/o power supply g14 gndio - 18 g4 i/o ground 91 g11 vddt0 - 44 n4,p4 3.3v / 5v power supply for transmitter driver vddt1 53 l4,m4 vddt2 56 l11,m11 vddt3 65 n11,p11 vddt4 116 a11,b11 vddt5 125 c11,d11 vddt6 128 c4,d4 vddt7 137 a4,b4 gndt0 - 47 n6,p6 analog gnd for transmitter driver gndt1 50 l6,m6 gndt2 59 l9,m9 gndt3 62 n9,p9 gndt4 119 a9,b9 gndt5 122 c9,d9 gndt6 131 c6,d6 gndt7 134 a6,b6 vdd0 - 19 h1 3.3v digital / analog core power supply vdda 90 h14 gnd0 - 20 h4 digital / analog core gnd gnda 89 h1
12 industrial temperature ranges octal t1/e1 short haul analog front end functional description overview the IDT82V2048L is a fully integrated octal short-haul analog front end (afe), which contains eight transmit and receive channels for use in either e1 or t1 applications. the raw sliced data (no retiming) can be output to the system. transmit equalization is implemented with low-imped- ance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. moreover, testing fuctions, such as jtag boundary scan is provided. the device is optimized for flexible soft- ware control through a serial or parallel host mode interface. hardware control is also available. figure 1 shows one of the eight identical chan- nels operation. t1/e1 mode selection t1/e1 mode selection configures the device globally. in hardware mode, the template selection pins: ts2, ts1 and ts0 determine whether the operation mode is t1 or e1 (refer to table 4). in software mode, the transmit template select register (primary register: 11hex) determines whether the operation mode is t1 or e1. system interface the system interface of each channel operates in dual rail mode with data recovery, that is with raw data slicing only and without clock recovery. the dual rail interface consist of tdpn, tdnn, tclkn, rdpn, rdnn and rcn. data transmitted from tdpn and tdnn appears on ttipn and tringn at the line interface. the interface of the afe is shown in figure 3 . pin rdpn and rdnn, in the condition, are raw rz slice output and internaly connected to an xor which is fed to the rcn output for exter- nal clock recovery applications. system interface configuration for normal transmit and receive operation, the device is configured as follows: in host mode, mclk can be either clocked or pulled high. if mclk is pulled high, tclk1 has to be provided for proper device operation. in addition, register bits e-afe in the extended register have to be set to ?1? to ensure proper device operation (see extended register description for details). in hardware mode, mclk has to be pulled high and tclk1 has to be provided for proper device operation. depending on the state of tclk1 and tclkn, the transmiter will transmit all ones (tao), will go into power down, or will go into high impedance. the status of tclk1 and tclkn has no effect on the receive paths. by setting mclk low, all the receive paths are powered down. table 1 summarizes the different combinations between mclk and tclkn. table 1 system interface configuration mode: host or mclk tclk1 tclkn afen in interface hardware e-afe transmit and receive normal operation host (1) only clocked clocked clocked 1 normal operation host or high clocked clocked dc (3) normal operation hardware (2) transmit interface modes host only clocked high ( 16 mclk) 1 transmit all one (tao) signals to line side in corresponding transmit channel host only clocked low ( 64 mclk) 1 corresponding transmit channel is set to power down mode host or high/low tclkn high dc transmit all one (tao) signals to line side in corresponding hardware tclk1 is ( 16 tclk1) transmit channel host or high/low clocked tclkn low dc corresponding transmit channel is set to power down mode hardware ( 64 tclk1) host or high/low tclk1 not dc dc all eight transmitter (ttipn & (tringn) in high impedance hardware available (h/l) state receive interface modes host or low the receive path is not affected hardware by the status of tclk1 or tclkn dc all receive paths are powered down notes: 1. in host mode bits afen in e-afe must be set to 1 for proper operation (see extended register description for detail). 2. in hardware mode mclk must be pulled high and tclk1 provided for proper operation. 3. dc = don?t care
13 industrial temperature ranges octal t1/e1 short haul analog front end clock edges the active edge of rcn and sclk (serial interface clock) are also selectable. if pin clke is low, the active edge of rcn is the rising edge, as for sclk, that is falling edge. on the contrary, if clke is high, the active edge of rcn is the falling edge and that of sclk is rising edge. pins rdpn, rdnn, and sdo are always active high, and those output signals are valid on the active edge of rcn and sclk respectively. see table 2 for details. pin clke is used to set the active level for rdpn/rdnn raw slicing output: high for active high polarity and low for active low. it should be noted that data on pin sdi are always active high and is sampled on the rising edge of sclk. the data on pin tdp or tdn are also always active high but is sampled on the falling edge of tclk, despite the level on clke. receiver in receive path, the line signals couple into rringn and rtipn via a transformer and are converted into rz digital pulses by a data slicer. adaptation for attenuation is achieved using an integral peak detector that sets the slicing levels. the recovered data clocked out of pin rdpn/rdnn in a undecoded dual rail rz. loss of signal is detected. this change in status may be enabled to generate an interrupt. peak detector and slicer the slicer determines the presence and polarity of the received pulses. the raw positive slicer output appears on rdpn while the negative slicer output appears on rdnn. the slicer circuit has a built-in peak detec- tor from which the slicing threshold is derived. the slicing threshold is de- fault to 50% (typical) of the peak value. signals with an attenuation of up to 12db (from 2.4v) can be recov- ered accurately by the receiver. to provide immunity from impulsive noise, the peak detectors are held above a minimum level of 0.150 v typically, despite the received signal level. figure 3. analog front end (afe) interface ? ? rtipn rringn ttipn tringn slicer peak detector line driver waveform shaper transmit all ones los detector one of eight identical channels 6527 drw04 tclkn tdnn losn rcn rdpn rdnn tdpn rdp an rdn pin clke rc active edge slicer output sdo table 2 active clock edge and active level low rc active high active low sclk active high high rc active high active high sclk active high
14 industrial temperature ranges octal t1/e1 short haul analog front end data recovery the analog line signals are converted to rz digital bit streams on the rdpn/rdnn pins and internally connected to an xor which is fed to the rcn output for external clock recovery applications. loss of signal (los) detection the loss of signal detector monitors the amplitude and density of the received signal on receiver line before the transformer (measured on port a, b in figure 6). the loss condition is reported by pulling pin los to high. in the same time, los alarm registers track los condition. when los is detected or cleared, and interrupt will be generated if not masked. in host mode, the detection supports the ansi t1.231 mode and itu-g.775 and etsi 3600233 for e1 mode. in hardware mode, it only supports the itu- g.775 and ansi t1.231 specification. table 3 summarizes the conditions of los. the los condition is cleared upon detecting the signal level exceeds 540mv. during los, the rdpn/rdnn output the sliced data when bit aise in register gcf is 0 or output all ones as ais (alarm indication signal) when bit aise is set to 1; the rcn is replaced by mclk only if the aise is set. transmitter in transmit path, nrz (non return to zero) data is clocked into the de- vice on tdpn and tdnn. the data is sampled into the device on falling edges of tclkn. the shape of the pulses are user programmable to en- sure that the t1/e1 pulse template is met after the signal is passed through different cable lenghts or types. table 3 los condition standard signal on ansi t1.231 for t1 g.775 for e1 etsi 300233 for e1 pin losn los continuous 175 32 2048(1ms) intervals h detected amplitude below typ. 310mv (vpp) below typ. 310mv (vpp) below typ. 310mv (vpp) los 12.5% (16 marks in a sliding 12.5% (4 marks in a sliding 12.5% (4 marks in a sliding density 128-bit period) with no more 32-bit period) with no more 32-bit period) with no more l cleared than 99 continuous zeros. than 15 continuous zeros. than 15 continous zeros amplitude exceed typ. 540mv (vpp) exceed typ. 540mv (vpp) exceed typ. 540mv (vpp)
15 industrial temperature ranges octal t1/e1 short haul analog front end waveform shaper t1 pulse template, specified in the dsx-1 cross-connect by ansi t1.102 is illustrated in figure 4. the device has built-in transmit waveform templates, corresponding to 5 levels of pre-equalization for cable of a length from 0 to 655ft with each increment of 133ft. e1 pulse template, specified in itu-t g.703, is shown in figure 5. the device has built-in transmit waveform templates for cable of 75 ? or 120 ? . any one of the six built-in waveform can be chosen in both hardware mode and host mode. setting the pins ts[2:0] as shown in table 4 in hardware mode, is selecting the required waveform template for all the transmitters. in host mode, the waveform template can be configured on per-chan- nel basis. bit tsia[2:0] in register tsia is used to select the channel and bit ts[2:0] in register ts is to select the required waveform template. refer to register descritption for details. the built-in waveform shaper uses an internal high frequency clock which is 16xmclk as clock reference. this function will be bypassed when mclk is unavailable. -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplit ude 6527 drw05 figure 4. dsx-1 waveform template -300 -200 -100 0 100 200 300 time (ns) -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 normalized amplitude 6527 drw06 figure 5. cept waveform template ts2 ts1 ts0 service clock rate cable length maximum cable loss (db) 1 table 4 built-in waveform template selection 0 0 0 e1 2.048mhz 120 ? / 75 ? cable - - 0 0 1 reserved 010 0 1 1 0 - 133ft. abam 0.6 1 0 0 1.544 133 - 266ft. abam 1.2 1 0 1 t1 mhz 266 - 399ft.abam 1.8 1 1 0 399 - 533ft. abam 2.4 1 1 1 533 - 655ft. abam 3.0 note: 1. maximum cable loss at 772 khz
16 industrial temperature ranges octal t1/e1 short haul analog front end line interface circuitry the transmit and receive interce rtip/rring connections provide a matched interface to the cable. figure 6 shows the appropriate external components to connect with the cable for one transmit/receive channel. ta- ble 6 summarizes the component values based on the specific application. transmit driver power supply all transmit driver power supplies must be 5.0v or 3.3v. in e1 mode, despite of the power supply voltage, the 75 ? /120 ? lines are driven through 9.5 ? series resistors and a 1:2 transformer. in t1mode,when 5.0v is selected, 100 ? lines are driven through 9.1 ? series resistors and a 1:2 transformer. when 3.3v is selected, 100 ? lines are driven through a 1:2 transformer. to optimize the power con- sumption of the device, series resistors are removed in this case. in harsh cable enviroments, series resistors are required to improve the transmit return loss performance and protect the device from surges coupling into the device. electrical specification @ 25 c part no. turns ratio (pri: sec 2%) oci. @ 25 c (mh min) l l (mh max) c w/w (pf max) package/ schematic table 5 transformer specifications std temp. ext temp transmit receive transmit receive transmit receive transmit receive t1124 t1114 1:2ct 1ct:2 1.2 1.2 .6 .6 35 35 tou/3 e1 t1 component 750 ? ? ? ? ? coax 120 ? ? ? ? ? coax twisted pair 100 ? ? ? ? ? twisted pair vddt = 5.0v 100 ? ? ? ? ? twisted pair vddt = 3.3v table 6 external components values r t 9.5 ? 1% 9.5 ? 1% 9.1 ? 1% 0 ? r r 9.31 ? 1% 15 ? 1% 12.4 ? % 12.4 ? 1% cp 2200pf 1000pf d1 - d4 nihon inter electronics - ep05q03l, 11eqs03l, ec10qs04, ec10qs03l; motorola - mbr0540t1 0.22 f ? ? ? ?? r x line 1k ? r r r r ? ? t x line r t r t rtipn rringn tringn ttipn ? ? 0.1 f gndtn vdddn vddt IDT82V2048L one of eight identical channels vddt d2 d1 2 : 1 (1) 2 : 1 (1) 1k ? cp 68 f (3) (2) a b vddt d4 d3 vddt d8 d7 6527 drw07 figure 6. external transmit/receive line circuitry notes: 1. pulse t1124 transformer is recommened to use in standard (std) operating temperature range (0 to 70 c), while pulse t1114 is recommended to use in extended (ext) operating temperature range is -40 to +85 c. see transformer specification table for details. 2. typical value. adjust for actual board parasitics to obtain optium return loss. 3. common decoupling capacitor for all vddt and gndt pins. notes: 1. pulse t1124 transformer is recommened to us in standard (std) operating temperature range (0 to 70 c), while pulse t1114 is recommended to use in extended (ext) operating temperature range is -40 to +85 c. 2. typical value. adjust for actual board parasitics to obtain optium return loss. 3. common decoupling capacitor for all vddt and gndt pins.
17 industrial temperature ranges octal t1/e1 short haul analog front end power driver failure monitor an internal power driver failure monitor (dfm), parallelly connected with ttipn and tringn, can detect short circuit failure in the secondary side of transformer. this feature is available only in host mode with no trans- mit series resistors, i.e. in t1mode with vddt is 3.3v. bit scpb in register gcf decides whether the output driver short- circuit protection is enabled. (refer to programming information ). when it is enabled, the driver?s output current is limited to 150ma (typical). line protection in transmit side, the schottky diodes d1-d4 are required to protect the line driver and improve the design robustness. in receive side, the series resistors of 1k ? are used to protect the receiver against current surges coupled in the device. it does not affect the receiver sensitivity, since the receiver impedance is as high as 120k ? typically. hitless protection switching (hps) the IDT82V2048L tranceiver include an output driver high-z feature for t1/e1 redundancy applications. this feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. details of hps is described in application note an-357. reset writing register rs can cause software reset by initiating about 1ms reset cycle. the operation set all the registers to their default value. power up during power up, an internal reset signal sets all the registers to de- fault values. this procedure takes at least 2 machine cycles. power down each transmitter channel will be power down by pulling pin tclkn to low for more than 64 mclk cycles. (if mclk is available) or about 30us (when mclk is not available). in host mode, each transmitter channel will also be power down by setting bit tpdnn in e-tpdnn to 1. all receivers will power down when mclk is low. in host mode, when mclk is clocked or high, setting bit rpdnn in e-rpdnn to ?1? will configure the corresponding receiver to power down. interface with 5v logic the IDT82V2048L can interface directly with 5v family devices. the internal input pads are tolerant to 5v output from ttl and cmos family devices. transmit all ones in hardware mode, the taos mode is set by pulling tclkn high for more that 16 mclk cycles. in host mode, taos mode is set by program- ming register tao . in addition, automatic tao signals are inserted by setting register atao when loss of signal occurs. note that the taos generator adopts mclk as a timing reference. in order to assure that the output fre- quency is within specification limits, mclk must have the applicable stability. ? ? rtipn rringn ttipn tringn slicer peak detector line driver waveform shaper transmit all ones los detector one of eight identical channels 6527 drw08 tclkn tdnn losn rcnn rdpn rdnn tdpn figure 7. taos data path
18 industrial temperature ranges octal t1/e1 short haul analog front end host interfaces the host interface provides access to read and write the registers in the device. the interface consists of serial host interface and parallel host interface. by pulling mode2 to vddio/2 or to high, the device can be set to work in serial mode and in parallel mode respecively. in host mode op- eration, extended register e-afe has to be set to ff h for proper device operation. see extended register description for details. parallel host interface the interface is compatible with motorola or intel host. pins mode1 and mode0 are used to select the operating mode of the parallel host inter- face. when pin mode1 is pulled to low, the host uses separate address bus and data bus. when high, multiplexed address/data bus is used. when pin mode0 is pulled to low, the parallel host interface is configured for motorola compatible hosts. when high, for intel compatible hosts. this is well described in the pin description . the host interface pins in each operation mode is tabulated in table 6. serial host interface by pulling pin mode2 to vddioi/2, the device operates in the serial host mode. in this mode, the registers are accessible through a 16-bit word which contains an 8-bit command/address byte (bit r/ w and 5-address-bit a1-a5, a6 and a7 are ignored) and a subsequent 8-bit data byte (d0-d7). when bit r/ w is 1, data is read out at pin sdo. when bit r/ w is 0, data is written into pin sdi to the register which is indicated by address bits a5-a1. mode[2:0] host interface generic control, data and output pin name 100 non-multiplexed motorola interface cs , ack , ds , r/ w , as , a[4:0], d[7:0], int 101 non-multiplexed intel interface cs , rdy, wr , rd , ale, a[4:0], d[7:0], int 110 multiplexed motorola interface cs , ack , ds , r/ w , as , ad[7:0], int 111 multiplexed intel interface cs , rdy, wr , rd , ale, ad[7:0], int table 7 parallel host interface pins a1 a3 a2 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 r/ w d0 d1 d2 d3 d4 d5 d6 d7 a7 input data byte address/command byte high impedance driven while r/ w =1 sdi sdo sclk cs 1 22 6527 drw09 figure 8. serial host mode timing
19 industrial temperature ranges octal t1/e1 short haul analog front end interrupt handling interrupt sources there are two kinds of interrupt sources: 1. status change in the los (loss of signal) status register (04h). the analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in los which indicates presence or absence of a los condition. 2. status change in the df (driver fault) status register (05h). the automatic power driver circuit continuously montiors the output drivers sig- nal to update the specific bit in dfm which indicates presence or absence of a secondary driver short circuit condition. interrupt enable the IDT82V2048L provides a latched interrupt output ( int ) and the four kinds of interrupts are all reported by this pin. when the interrupt maske register ( losm, dfm ) is set to ?1?, the interrupt status register ( losi, dfi ) is enabled repectively. whenever there is a transition (?0? to ?1? to ?0?) in the corresponding status register, the interrupt status register will change into ?1?, which means an interrupt occurs, and there will be a transition from high to low on int . an external pull-up resistor of approxi- mately 10k ? is required to support the wire-or operation of int . when any of the four interrupt mask registers is set to ?0? (the power-on default value is ?0?), the corresponding interrupt status register is disabled and the transition on status register is ignored. interrupt clearing when an interrupt occurs, the interrupt status registers ( losi,dfi , are read to identify the interrupt source. and these registers will be cleared to ?0? after the corresponding status register ( los, df ) being read. the status registers will be cleared once the corresponding conditions are met. pin int is pulled high when there are no pending interrupt left. the interrupt handling in the interrupt service routine is showed figure 9. g.772 monitoring the eight channels of IDT82V2048L can all be configured to work as regular transceivers. in applications using only seven channels (channels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels? inputs or outputs on the line side. the monitoring is non-intrusive per itu-t g.772. figure 10 shows the monitoring principle. the receiver or transmitter path to be monitored is configured by pin mc[0:3] in hard- ware mode or by pmon in host mode (refer to programming informa- tion for details). the signal which is monitored goes through the clock and data recov- ery circuit of channel 0. the monitored clock can output on rcn0 which can be used as a timing interfaces derived from e1 signal. the monitored data can be observed digitally at the output pin rcn0, rd0/rdp0 and rdn0. los detector is still in use in channel 0 for the monitored signal. in monitoring mode, channel 0 can be configured to the remote loopback. the signal which is being monitored will output on ttip0 and tring0. the output signal can then be connected to a standard test equipment with an e1 electrical interface for non-intrusive monitoring. service the interrupt read interrupt status register read corresponding status register interrupt allowed interrupt condition exist? yes no 6527 drw10 figure 9. interrupt service routine
20 industrial temperature ranges octal t1/e1 short haul analog front end slicer peak detector line driver waveform shaper los detector channel n ( 7 > n > 1 ) rtipn rringn ttipn tringn losn rcn rdpn dnn r tclkn tdnn tdpn g.772 monitor transmit all ones slicer peak detector line driver waveform shaper los detector channel 0 los0 rc n rdp0 rdn0 tclk0 tdn0 tdp0 transmit all ones rtip0 rring0 ttip0 tring0 6527 drw11 figure 10. monitoring principle
21 industrial temperature ranges octal t1/e1 short haul analog front end programming information register list and map there are 17 primary registers (including an address pointer control register), including 4 extended registers in the device (1) . whatever the control interface is, 5 address bits are used to set the registers. in non-multiplexed parallel interface mode, the five dedicated ad- dress bits are a[4:0]. in multiplexed parallel interface mode, ad[4:0] carries the address information. in serial interface mode, a[5:1] are used to ad- dress the register. the address pointer control register ( addp ), ad- dressed as 11111 of 1f hex, switches between primary registers bank and extended registers bank. by setting the content of addp to aah, the 5 address bits point to the extended register bank, that is, 16 extended registers are then available to access. by clearing addp, the primary registers are accessible again. table 8 primary register list address serial parallel hex interface interface register r/w explanation a7-a1 a7-a0 00 xx00000 xxx00000 id r device id register 01 xx00001 xxx00001 reserved 02 xx00010 xxx00010 03 xx00011 xxx00011 tao r/w transmit all one code configuration register 04 xx00100 xxx00100 los r loss of signal status register 05 xx00101 xx00101 df r driver fault status register 06 xx00110 xxx001 10 losm r/w los interrupt mask register 07 xx00111 xxx00111 dfm r/w driver fault interrupt mast register 08 xx01000 xxx01000 losi r los interrupt status register 09 xx01001 xxx01001 dfi r driver fault interrupt status register 0a xx01010 xxx01010 rs w software reset register 0b xx01011 xxx01011 pmon r/w performance monitor configuration register 0c xx01100 xxx01100 reserved 0d xx01101 xxx01101 lac r/w los criteria configuration register 0e xx01110 xxx01110 a tao r/w automatictao configuration register 0f xx01111 xxx01111 gcf r/w global configuration register 10 xx10000 xx10000 tsia r/w indirect address register for transmit template select 11 xx10001 xxx10001 ts r/w t ransmit template select register 12 xx10010 xxx10010 oe r/w output enable configuration register 13 xx10011 xxx10011 14 xx10100 xxx10100 15 xx10101 xxx10101 16 xx10110 xxx10110 17 xx10111 xxx10111 18 xx11000 xxx11000 19 xx11001 xx11001 reserved 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xxx11101 xxx11101 1e xx11110 xxx11110 1f xx11111 xxx11111 addp r/w address pointer control register for switching between primary register bank and extended register bank note: 1. in host mode operation, extended register e-afe has to be set to ff h for proper device operation. see extended register description for details.
22 industrial temperature ranges octal t1/e1 short haul analog front end address serial parallel hex interface interface register r/w explanation a7-a1 a7-a0 00 xx00000 xxx00000 reserved 01 xx00001 xxx00001 reserved 02 xx00010 xxx00010 e-afe (1) r/w afe enable register 03 xx00011 xxx00011 e-rdpn r/w receiver n powerdown enable/disable register 04 xx00100 xxx00100 e-tpdn r/w transmitter n powerdown enable/disable register 05 xx00101 xxx00101 reserved 06 xx00110 xxx00110 07 xx00111 xxx001 11 e-equa r/w enable equalizer enable/disable register 08 xx01000 xxx01000 09 xx01001 xxx01001 0a xx01010 xxx01010 0b xx01011 xxx01011 reserved 0c xx01100 xxx01100 0d xx01101 xx011010 0e xx01110 xxx01110 0f xx01111 xxx01111 10 xx1000 xxx10000 11 xx10001 xxx10001 12 xx10010 xxx10010 13 xx10011 xxx10011 14 xx10100 xxx10100 15 xx10101 xxx10101 16 xx10110 xxx10110 17 xx10111 xx101111 test 18 xx11000 xxx11000 19 xx11001 xxx11001 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xx11101 xxx11101 1e xx11110 xxx11110 1f xx11110 xxx11110 addp r/w address pointer control register for switching between primary register bank and extended register bank. note: 1. in host mode operation, extended register e-afe has to be set to ff h for proper device operation. see extended register description for details. table 9 extended (indirect address mode) register list
23 industrial temperature ranges octal t1/e1 short haul analog front end table 10 primary register map register address b7 b6 b5 b4 b3 b2 b1 b0 r/w default id 00 hex id 7 id 6 id 5 id 4 id 3 id 2 id 1 id 0 r/wrrr rr r r r default 0 0 0 1 0 0 0 0 tao 03 hex tao 7 tao 6 tao 5 tao 4 tao 3 tao 2 tao 1 tao 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 los 04 hex los 7 los 6 los 5 los 4 los 3 los 2 los 1 los 0 r/wrrr rr r r r default 0 0 0 0 0 0 0 0 df 05 hex df 7 df 6 df 5 df 4 df 3 df 2 df 1 df 0 r/wrrr rr r r r default 0 0 0 0 0 0 0 0 losm 06 hex losm 7 losm 6 losm 5 losm 4 losm 3 losm 2 losm 1 losm 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dfm 07 hex dfm 7 dfm 6 dfm 5 dfm 4 dfm 3 dfm 2 dfm 1 dfm 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 losi 08 hex losi 7 losi 6 losi 5 losi 4 losi 3 losi 2 losi 1 losi 0 r/wrrr rr r r r default 0 0 0 0 0 0 0 0 dfi 09 hex dfi 7 dfi 6 dfi 5 dfi 4 dfi 3 dfi 2 dfi 1 dfi 0 r/wrrr rr r r r default 0 0 0 0 0 00 0 0 rs 0a hex rs 7 rs 6 rs 5 rs 4 rs 3 rs 2 rs 1 rs 0 r/wwww ww w w w default 1 1 1 1 1 1 1 1 pmon 0b hex - - - - mc 3 mc 2 mc 1 mc 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lac 0d hex lac 7 lac 6 lac 5 lac 4 lac 3 lac 2 lac 1 lac 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atao 0e h e x ata 7 ata 6 ata 5 ata 4 ata 3 ata 2 ata 1 ata 0 r/w rw r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 gcf 0f hex - aise scpb code jadp jabw jacf 1 jacf 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 tsia 10 hex 0 0 0 0 0 tsia 2 tsia 1 tsia 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ts 11 hex - - - - - ts 2 ts 1 ts 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 oe 12 hex oe 7 oe 7 oe 7 oe 7 oe 7 oe 7 oe 7 oe 7 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 addp 1f hex addp 7 addp 6 addp 5 addp 4 addp 3 addp 2 addp 1 addp 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
24 industrial temperature ranges octal t1/e1 short haul analog front end table 11 extended (indirect address mode) register map register address b7 b6 b5 b4 b3 b2 b1 b0 r/w default e-afe (1) 02 hex afe 7 afe 6 afe 5 afe 4 afe 3 afe 2 afe 1 afe 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 e-rdpn 03 hex rpdn 7 rpdn 6 rpdn 5 rdpn 4 rdpn 3 rdpn 2 rdpn 1 rdpn 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 e-tpdn 04 hex tpdn 7 tpdn 6 tpdn 5 tpdn 4 tpdn 3 tpdn 2 tpdn 1 tpdn 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 e-equa 07 hex equa 7 equa 6 equa 5 equa 4 equa 3 equa 2 equa 1 equa 0 r/w r r r r r r r r default 0 0 0 0 0 0 0 0 addp 1f hex addp 7 addp 6 addp 5 addp 4 addp 3 addp 2 addp 1 addp 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 note: 1. in host mode operation, extended register e-afe has to be set to ff h for proper device operation. see extended register description for details.
25 industrial temperature ranges octal t1/e1 short haul analog front end register description primary register description id : device id register (r, address = 00 hex) symbol position default description id[7:0] id.7.0 10 h an 8-bit word is pre-set into the device as the identification and revision number. this number is different with the functional changes and is mask programmed. tao : transmit all one code configuration register (r/w, address = 03 hex) symbol position default description tao[7:0] tao.7.0 00 h 0 = normal operation (default) 1 = transmit all one code. los : loss of signal status register (r, address = 04 hex) symbol position default description los[7:0] los.7.0 00 h 0 = normal operation (default) 1 = loss of signal detected. df : driver fault status register (r, address = 05 hex) symbol position default description df[7:0] df.7.0 00 h 0 = normal operation (default) 1 = driver fault detected. note that df is available only in t1 mode with 3.3v (without transmit series resistors). losm : loss of signal interrupt mask register (r/w, address = 06 hex) symbol position default description losm[7:0] losm.7.0 00 h 0 = los interrupt is not allowed. (default) 1 = los interrupt is allowed. dfm : driver fault interrupt mask register (r/w, address = 07 hex) symbol position default description dfm[7:0] dfm.7.0 00 h 0 = driver fault interrupt is not allowed. (default) 1 = driver fault interrupt is allowed.
26 industrial temperature ranges octal t1/e1 short haul analog front end losi : loss of signal interrupt status register (r, address = 08 hex) symbol position default description losi[7:0] losi.7.0 00 h 0 = (default). or after los read operation. 1 = any transition on losn (corresponding losmn is set to 1). dfi : driver fault interrupt status register (r, address = 09 hex) symbol position default description dfi[7:0] dfi.7.0 00 h 0 = (default). or after df read operation. 1 = any transition on dfn (corresponding dfn is set to 1). rs : software reset register (w, address = 0a hex) symbol position default description rs[7:0] rs.7.0 ff h writing to this register will not change the content in this register but initiate a 1 s reset cycle, which means all the registers in the device are set to their default values. pmon : performance monitor configuration register (r/w, address = 0b hex) symbol position default description - pmon.7-4 0000 0 = normal operation (default) 1 = reserved. mc[3:0] monitoring configurations 0000 normal operation without monitoring. 0001 monitoring receiver 1. 0010 monitoring receiver 2. 0011 monitoring receiver 3. 0100 monitoring receiver 4. 0101 monitoring receiver 5. 0110 monitoring receiver 6.. 0111 monitoring receiver 7. mc[3:0] pmon.3-0 0000 1000 normal operation without monitoring. 1001 monitoring transmitter 1. 1010 monitoring transmitter 2. 1011 monitoring transmitter 3. 1100 monitoring transmitter 4. 1101 monitoring transmitter 5. 1110 monitoring transmitter 6. 1111 monitoring transmitter 7. lac : los criteria configuration register (r/w, address = 0d hex) symbol position default description lac[7:0] lac.7.0 00 h for e1 mode, the criteria is selected as below: 0 = g.775 mode. (default) 1 = etsi 300233 mode. for t1 mode, the los cirteria meets t1.231.
27 industrial temperature ranges octal t1/e1 short haul analog front end atao : automatice tao configuration register (r/w, address = 0e hex) symbol position default description atao[7:0] atao.7.0 00 h 0 = no automatic tao (default) 1 = automatic transmit all ones to the line side on los. gcf: global configuration register (r/w, address = 0f hex) symbol position default description - gcf.7-6 0 0 = normal operation (default) 1 = reserved. scpb gcf.5 0 short circuit protection enable. 0 = short circuit protection is enabled. (default) 1 = short circuit protection is disabled. - gcf.4-0 0 0 = normal operation (default) 1 = reserved. tsia : indirect address register for transmit template select registers (r/w, address = 10 hex) symbol position default description - tsia.7 00000 0 = normal operatin (default) 1 = reserved. tsia[2:0] channel tsia[2:0] channel 000 0 100 4 tsia[2:0] tsia.2-0 000 001 1 101 5 010 2 110 6 011 3 111 7
28 industrial temperature ranges octal t1/e1 short haul analog front end ts : transmit template select register (r/w, address = 11 hex) symbol position default description - ts.7.3 00000 0 = normal operatin (default) 1 = reserved. ts[2:0] select one of eight built-in transmit template for different applications. t s[2:0] mode cable length 000 e1 75 ? coaxial cable/120 ? twisted pair cable. 001 ts[2:0] ts.2-0 000 010 reserved 011 t1 0 - 133 ft. 100 t1 133 - 266 ft. 101 t1 266 - 399 ft. 110 t1 399 - 533 ft. 111 t1 533 - 655 ft. oe : output enable configuration register (r/w, address = 12 hex) symbol position default description oe[7:0] oe.7.0 00 h 0 = transmit drivers enabled. (default) 1 = transmit drivers placed in high impedance state. addp : address pointer control register (r/w, address = 1f hex) symbol position default description two kinds of configuration in this register can be set to switch between primary register bank and extended register bank. when power up, the address pointer will point to the top address of primary addp[7:0] addp.7-0 00 h register bank automatically. 00h = the address pointer points to the top address of primary register bank. (default). aah = the address pointer points to the top address of extended register bank.
29 industrial temperature ranges octal t1/e1 short haul analog front end extended register description e-afe : afe enable selection register (r/w, extended address = 02 hex) symbol position default description afe[7:0] afe.7-0 00 h 1 0 = reserved (default) 1 = afe mode enabled note: 1. in host mode afe[7:0] must be set to ff h for proper device operation e-rpdn : receiver powerdown register (r/w, extended address = 03 hex) symbol position default description rpdn[7:0] rpdn.7-0 00 h 0 = normal operation (default) 1 = power down in receiver n. e-tpdn : transmitter n powerdown register (r/w, extended address = 04 hex) symbol position default description 0 = normal operation (default) tpdn[7:0] tpdn.7-0 00 h 1 = power dow n in transmitter n (the corresponding transmit output driver enters a low power high impedance mode). note that transmitter n is power down when either pin tclkn is pulled to low ot tpdnn is set to 1. e-equa : receive equalizer enable/disable register (r/w, extended address = 07 hex) symbol position default description 0 = normal operation (default) equa[7:0] equa.7-0 00 h 1 = equalizer in receiver n enabled, which can improve the receive performance when transmission lenghts is more than 200 m.
30 industrial temperature ranges octal t1/e1 short haul analog front end ieee std 1149.1 jtag test access port the IDT82V2048L supports the digital boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture consists of data and instruction regis- ters plus a test access port (tap) controller. control of the tap is acheived through signals applied to the test mode select (tms) and test clock (tck) input pins. data is shifted into the registers via the test data input (tdi) pin, and shifted out of the registers via the test data output (tdo) pin. both tdi and tdo are clocked at a rate determined by tck. the jtag boundary scan registers includes bsr (boundary scan registers), idr (device identification register), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to figure 11 for architecture. jtag instructions and instruction register (ir) the ir (instruction register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table 8 for details ofthe codes and the instructions related. bsr (boundary scan register) idr (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select tristate enable tap (test access port) controller parallel latched output digital output pins digital input pins 6527 drw12 figure 11. jtag architecture
31 industrial temperature ranges octal t1/e1 short haul analog front end table 12 instruction register description ir code instruction comments extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register using the capture-dr state. the 000 sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample / preload the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. the normal path between IDT82V2048L logic and the i/o pins 100 is maintained. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dt state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. 110 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device?s identification code can then be shifted out using the shift-dr state. 111 bypass the bypass instruction shifts data from input tdi and tdo with one tck clock period delay. the instruction is used to bypass the device. table 14 boundary scan register description bit no. comments 0 set to ?1? 1-11 producer number 12-27 part number 28-31 device revision bypass register (br) the br consists of a single bit, it can provide a serial path between the tdi input and tdo output, bypassing the bsr to reduce test access times. boudary scan register (bsr) the bsr can apply and read test patterns in parallel to or from all the digital i/o pins. the bsr is a 98 bits long shift register and is initialized and read using the instruction extest or sample/preload. each pin is re- lated to one or more bits in the bsr. please refer to table 15 for details of bsr bits and their functions. test access port controller the tap controller is a 16-state synchrnous state machine. figure 6 shows its state diagram. a description of each state follows. note that the figure contains two main branches to access either the data or instruction registers. the value shown next to each state transition in this figure states the value present at tms at each rising edge of tck. please refer to table 14. jtag data register device identification register (idr) the idr can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or revision number that has been used in the system under test. the idr is 32 bits long and is partitioned as in table 14 . data from the idr is shifted out to tdo lsb first. table 13 device identification register description bit no. bit symbol pin signal type comments 0 pout0 d0 i/o 1 pin0 d0 i/o 2 pout1 d1 i/o 3 pin1 d1 i/o 4 pout2 d2 i/o 5 pin2 d2 i/o 6 pout3 d3 i/o 7 pin3 d3 i/o 8 pout4 d4 i/o 9 pin4 d4 i/o 10 pout5 d5 i/o 11 pin5 d5 i/o 12 pout6 d6 i/o 13 pin6 d6 i/o 14 pout7 d7 i/o
32 industrial temperature ranges octal t1/e1 short haul analog front end table 14 boundary scan register description (continued) bit no. bit symbol pin signal type comments 15 pin7 d7 i/o 16 pios n/a - controls pin d7-0 when ?0? , the pins are configured as outputs. the output values to the pins are set in pout7-0. when ?1?, the pins are high-z. the input value to the pins are read in pin7-0 17 tclk1 tclk1 i 18 tdp1 tdp1 i 19 tdn1 tdn1 i 20 rc1 rc1 o 21 rdp1 rdp1 o 22 rdn1 rdn1 o 23 hzen1 n/a - controls pin rdp1, rdn1 and rc1 when ?0?, the outputs are enabled on the pins when ?1?, the pins are high-z. 24 los1 los1 o 25 tclk0 tclk0 i 26 tdp0 tdp0 i 27 tdn0 tdn0 i 28 rc0 rc0 o 29 rdp0 rdp0 o 30 rdn0 rdn0 o 31 hzen0 n/a - controls pin rdp0, rdn0 and rc0. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z 32 los0 los0 o 33 mode1 mode1 i 34 los3 los3 o 35 rdn3 rdn3 o 36 rdp3 rdp3 o 37 hzen3 n/a - controls pin rdp3, rdn3 and rc3. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z 38 rc3 rc3 o 39 tdn3 tdn3 i 40 tdp3 tdp3 i 41 tclk3 tclk3 i 42 los2 los2 o 43 rdn2 rdn2 o 44 rdp2 rdp2 o 45 hzen2 n/a - controls pin rdp2, rdn2 and rc2. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z 46 rc2 rc2 o 47 tdn2 tdn2 i 48 tdp2 tdp2 i 49 tclk2 tclk2 i 50 int int o 51 ack ack o 52 sdordys n/a - control pin ack. when ?0?, the outputs is enabled on pin ack. when ?1?, the pin is high-z. 53 wrb ds i 54 rdb r/ w i 55 ale ale i
33 industrial temperature ranges octal t1/e1 short haul analog front end table 14 boundary scan register description (continued) bit no. bit symbol pin signal type comments 56 csb cs i 57 mode0 mode0 i 58 tclk5 tclk5 i 59 tdp5 tdp5 i 60 tdn5 tdn5 i 61 rc5 rc5 o 62 rdp5 rdp5 o 63 rdn5 rdn5 o 64 hzen5 n/a - controls pin rdp5, rdn5 and rc5. when ?0?, the output are enabled on the pins. when ?1?, the pins are high-z. 65 los5 los5 o 66 tclk4 tclk4 i 67 tdp4 tdp4 i 68 tdn4 tdn4 i 69 rc4 rc4 o 70 rdp4 rdp4 o 71 rdn4 rdn4 o 72 hzen4 n/a - controls pin rdp4, rdn4 and rc4. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 73 los4 los4 o 74 oe oe i 75 clke clke i 76 los7 los7 o 77 rdn7 rdn7 o 78 rdp7 rdp7 o 79 hzen7 hzen7 - controls pin rdp7, rdb7 and rc7. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 80 rc7 rc7 0 81 tdn7 tdn7 i 82 tdp7 tdp7 i 83 tclk7 tclk7 i 84 los6 los6 o 85 rdn5 rdn5 o 86 rdp6 rdp6 o 87 hzen n/a - controls pin rdp6, rdn6 and rc6. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 88 rc6 rc6 o 89 tdn6 tdn6 i 90 tdp6 tdp6 i 91 tclk6 tclk6 i 92 mclk mclk i 93 mode2 mode2 i 94 a4 a4 i 95 a3 a3 i 96 a2 a2 i 97 a1 a1 i 98 a0 a0 i
34 industrial temperature ranges octal t1/e1 short haul analog front end table 15 tap controller state description state description test logic in this state, the test logic is diabled. the device is set to normal operation. during initialization, the device in itializes the instruction register reset with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset state when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. the device processor automatically en ters this state at power-up. run-test/idle this is a controller state between scan operations. once in this state, the controller remains in the state as lon g as tms is held low. the instruction register and all registers retain their previous state. when tms is high and a rising edge is applied to tck, the c ontroller moves to the select-dr state. select-dr-scan this is a temporary controller state and the instruction does not change in this state. the test data register s elected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves in to the capture- dr state and a scan sequence test data register is initiated. if tms is held high and a rising edge applied to tck, the contro ller moves to the select-ir-scan state. capture-dr in this state, the boundary scan register captures input pin data if the current instruction is extest or sample/prel oad. the instruction does not change in this state. the other data registers, which do not have parallel input, are not changed. when t he tap controller is in the state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr state if tms is low. . shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction shifts data on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr s tate if tms is low. exit1-dr this is a temporary state. when in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update- dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause- dr state. the test data register selected by the current instruction retains its previous value and the instruction does not c hange during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in t he serial path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin number memory from disk during applica tion of a long test sequence. the test data register selected by the current instruction retains its previous value and the instruc tin does not change during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state. exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update- dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift- dr state. the test dataregister selected by the current instruction retains its previous value and the instruction does not ch ange during this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to t he extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched into the parallel output of this register from the shift path on the falling edge of tck. the data held at the latched paralle l output changes only in the state. all shift-register stages in the test data register selected by the current instruction retain thier previo us value and the instruction does not change during this state. select-ir-scan this is temporary controller state. the test data register selected by the current instruction retains its previ ous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves into the capture-ir state, and a scan sequence fo r the instruction register is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-l ogic-reset state. the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of ?100? on th e rising edge of tck. this supports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain th eir value and the instruction does not changeduring this state. when the controller is in this state and a rising edge is applied to tck, th e controller enters the exit1-ir state if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instruction register is connected between tdi and tdo and shifts data one stage towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous v alue and the instruction does not change during this state and a rising edge is applied to tck, the controller enters the exit1-ir state if tms is held high, or remains in the shift-ir state if tms is held low.
35 industrial temperature ranges octal t1/e1 short haul analog front end table 15 tap controller state description (continued) state description exit1-ir this is temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller t o enter the update- ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause- ir state. the test data register selected by the current instruction retains its previous value and the instruction does not c hange during this state. pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. t he test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the cont roller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2 -ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update- ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift- ir state. the test data register selected by the current instruction retains its previous value and the instruction does not c hange this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous value. test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 6527 drw13 figure 12. jtag state diagram
36 industrial temperature ranges octal t1/e1 short haul analog front end absolute maximum rating symbol parameter min. max. unit vdda, vddd core power supply -0.5 4.0 v vddio0, vddio1 i/o power supply -0.5 4.0 v vddt0-7 transmit power supply -0.5 7.0 v vin input voltage, any digital pin gnd -0.5 5.5 v input voltage, any rtip and rring pin (1) gnd -0.5 vdda+0.5 v vdda+0.5 esd voltage, any pin (2) 2000 v lin transient latch-up current, any pin 100 ma input current, any digital pin (3) -10 10 ma dc input current, any analog pin (3) 100 ma pd maximum power dissipation in package 1.6 w ts storage temperature -65 +150 c caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to absolute maximuim rating conditions for extended periods may affect device reliability. notes: 1. referenced to ground 2. human body model 3. constant input current symbol parameter min. typ. max. unit vdda, vddd core power supply 3.13 3.3 3.47 v vddio i/o power supply 3.13 3.3 3.47 v vddt transmit power supply 3.3v 3.13 3.3 3.47 v 5v 4.75 5.0 5.25 v ta ambient operating temperature -40 25 85 c r l output load at ttip and tring 25 ? i vdd average core power supply current (1) 55 65 ma i vddio i/o power supply current (4) 15 25 ma i vddt average transmitter power supply current, t1 mode (1,2,3) 50% ones density data: 230 ma 100% ones density data: 440 note: 1. maximum power and current consumption over the full operating temperature and power supply voltage range. includes all cha nnels. 2. power consumption includes power absorbed by line load and external transmitter components. 3. t1 maximum values measured with maximum cable length (len = 111). typical values measured with typical cable lengths (len = 101). 4. digital output is driving 50pf load, digital input is within 10% of the supply rails. recommended operating conditions
37 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter len min. typ. max. (1,2) unit e1, 3.3v, 75 ? load 50% ones density data: 000 - 662 - mw 100% ones density data: 000 - 1100 1177 e1, 3.3v, 120 ? load 50% ones density data: 000 - 576 - mw 100% ones density data: 000 - 930 992 e1, 5.0v, 75 ? load 50% ones density data: 000 - 910 - mw 100% ones density data: 000 - 1585 1690 e1, 5.0v, 120 ? load 50% ones density data: 000 - 785 - mw 100% ones density data: 000 - 1315 1410 t1, 3.3v, 100 ? load (3) 50% ones density data: 101 - 820 - mw 100% ones density data: 111 - 1670 1792 t1, 5.0v, 100 ? load (3) 50% ones density data: 101 - 1185 - mw 100% ones density data: 111 - 2395 2670 notes: 1. maximum power and current consumption over the full operating temperature and power supply voltage range. includes all chan nels. 2. power consumption includes power absorbed by line load and external transmitter components. 3. t1 maximum values measured with maximum cable lengths (len = 111). typical values measured with typical cable lengths (len = 101). power consumption symbol parameter min. typ. max. unit v il input low level voltage mode2, dn pins 1/3 vddio-0.2 v all other digital inputs pins 0.8 v im input mid level voltage mode2, dn pins 1/3 vddio+0.2 1/2 vddio 2/3 vddio-0.2 v v ih input high voltage mode2, dn pins 2/3 vddio+0.2 v all other digital inputs pins 2.0 v ol output low level voltage (1) 0.4 v (iout=1.6ma) v oh output high level voltage (1) 2.4 vddio v (iout=400ma) v ma analog input quiescent voltage 1.33 1.4 1.47 v (rtip, rring pin while floating) i h input high level current 50 a (mode2, dn pin) i l input low level current 50 a (mode2, dn pin) i i input leakage current tms, tdi, trst 50 a all other digital input pins -10 10 a i zl high-z leakage current -10 10 a z oh output high impedance on (ttip, tring pins) 150 k ? dc characteristics note: 1. output drivers will output cmos logic levels into cmos loads.
38 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter min. typ. max. unit v o - p output pulse amplitudes (1) e1, 75 ? load 2.14 2.37 2.6 v e1, 120 ? load 2.7 3.0 3.3 v t1, 100 ? load 2.4 3.0 3.6 v vo-s zero (space) level e1, 75 ? load -0.237 0.237 v e1, 120 ? load -0.3 0.3 v t1, 100 ? load -0.15 0.15 c transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses 200 mv t pw output pulse width at 50% of nominal amplitude e1: 232 244 256 ns t1: 338 350 362 ns ratio of the amplitude of positive and negative pulses at the center of the pulse interval 0.95 1.05 rtx transmit return loss (2) e1, 75 ? 51 khz - 102 khz 15 db 102 khz - 2.048 mhz 15 db 2.048 mhz - 3.072 mhz 15 db e1, 120 ? 51 khz - 102 khz 15 db 102 khz - 2.048 mhz 15 db 2.048 mhz - 3.072 mhz 15 db t1 51 khz - 102 khz 15 db (vddt=5v) 102 khz - 2.048 mhz 15 db 2.048 mhz - 3.072 mhz 15 db td transmit path delay dual rail 3 u.i. i sc line short circuit current (3) 150 ma transmitter characteristics notes: 1. e1: measured at the line output ports; t1: measured at the dsx. 2. test at IDT82V2048L evaluation board. 3. measured at 2x9 5 ? series resistors and 1:2 transformer.
39 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter min. typ. max. unit att permissible cable attenuation 15 db (e1:@1024khz, t1:@772khz) ia input amplitude 0.1 0.8 vp sir signal to intereference ratio margin (1) -14 db sre data decision threshold (reference to peak input voltage) 50 db data slicer threshold 150 mv analog loss of signal (2) threshold: 310 mv hysteresis: 230 mv allowable consecutive zeros before los e1, g.775: 32 e1, etsi200233: 2048 t1, t1.231-1993 175 los reset clock recovery mode 12.5 % ones jrx p - p peak to peak intrinsic receive jitter (ja disabled) e1 (wide band): 0.0625 u.i. t1 (wide band): 0.0625 u.i zdm receiver differential input impedance 120 k ? zcm receiver common mode input impedance to gnd 10 k ? rrx receive return loss 51 khz - 102 khz 20 db 102 khz - 2.048 mhz 20 db 2.018 mhz - 3.072 mhz 20 db receive path delay dual rail 3 u.i. dc characteristics notes: 1. e1: per g.703, o.151 @6db cable attenuation. t1: @655ft. of 22abam cable. 2. the test circuit for this parameter is shown in figure 6. the analog signal is measured on the receiver line before the tr ansformer (port a and port b in figure 6). and the receive line is a t1/e1 cable simulator.
40 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter min. typ. max. unit mclk frequency e1: 2.048 mhz t1: 1.544 mclk tolerance -100 100 ppm mclk duty cycle 40 60 % transmit path tclk frequency e1: 2.048 mhz t1: 1.544 tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of oe low to driver high-z 1 ms delay time of tclk low to driver high-z 40 44 48 s receive path clock recovery capture range (1) e1 +/-80 ppm t1 +/-180 rcn duty cycle (2) 40 50 60 % t4 rcn pulse width (2) e1: 457 488 519 ns t1: 607 648 689 t5 rcn pulse width low time e1: 203 244 285 ns t1: 259 324 389 t6 rcn pulse width high time e1: 203 244 285 ns t1: 259 324 389 rise/fall time (3) t7 receive data setup time e1: 200 244 ns t1: 200 324 t8 receive data hold time e1: 200 244 ns t1: 200 324 t9 rdn/rdp pulse width (mclk = h) (4) e1: 200 244 ns t1: 300 324 transceiver timing characteristics notes: 1. relative to nominal frequency, mclk =+/- 100ppm. 2. rcn duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rcn duty cyc les are for worst case jitter conditions (0.2ui displacement for e1 per itu g.823) 3. for all digital outputs. c load = 15 pf. 4. clock recovery is disabled in this mode.
41 industrial temperature ranges octal t1/e1 short haul analog front end tdnn tdpn tclk t1 t2 6527 drw14 figure 13. transmit system interface timing rdnn rdpn rcn t4 t7 t6 t7 t5 t8 t8 (clke = 0) (clke = 1) rdpn rdnn 6527 drw15 figure 14. receive system interface timing
42 industrial temperature ranges octal t1/e1 short haul analog front end tck t1 t2 t3 tdo tms tdi t4 6527 drw16 figure 15. jtag interface timing jtag timing characteristics symbol parameter min typ max unit comments t1 tck period 200 ns t2 tms to tck setup time 50 ns tdi to tck setup time t3 tck to tms hold time 50 ns tck to tdi hold time t4 tck to tdo delay time 100 ns
43 industrial temperature ranges octal t1/e1 short haul analog front end parallel host interface timing characteristics symbol parameter min typ max unit comments t1 active rd pulse width 90 ns note 1 t2 active cs to active rd setup time 0 ns t3 inactive rd to inactive cs hold time 0 ns t4 valid address to inactive ale setup time (in multiplexed mode) 5 ns t5 invalid rd to address hold time (in non-multiplexed mode) 0 ns t6 active rd to data output enable time 7.5 15 ns t7 inactive rd to data high-z delay time 7.5 15 ns t8 active cs to rdy delay time 6 12 ns t9 inactive cs to rdy high-z delay time 6 12 ns t10 inactive rd to inactive int delay time 20 ns t11 address latch enable pulse width (in multiplexed mode) 10 ns t12 address latch enable to rd setup time (in multiplexed mode) 0 ns t13 address setup time to valid data time (in non-multiplexed mode) inactive ale to valid data time (in multiplexed mode) 18 32 ns t14 inactive rd to active rdy delay time 10 15 ns t15 active rd to active rdy delay time 30 85 ns t16 inactive ale to address hold time (in multiplexed mode) 5 ns intel mode read timing characteristics note: 1. the t1 is determined by the start time of the valid data when the rdy signal is not used.
44 industrial temperature ranges octal t1/e1 short haul analog front end int rdy d[7:0] a[7:0] ale(=1) rd cs t1 t2 t3 t5 t6 t7 t10 t13 address data out t15 6527 drw17 t14 t9 t8 figure 16. non-multiplexed intel mode read timing int rdy ad[7:0] ale rd cs t1 t2 t3 t6 t11 t12 address data out t15 t13 6527 drw18 t4 t16 t7 t14 t9 t10 t8 figure 17. multiplexed intel mode read timing
45 industrial temperature ranges octal t1/e1 short haul analog front end figure 18. non-multiplexed intel mode write timing figure 19. multiplexed intel mode write timing intel mode write timing characteristics symbol parameter min typ max unit comments t1 active wr pulse width 90 ns note 1 t2 active cs to active wr setup time 0 ns t3 inactive wr to inactive cs hold time 0 ns t4 valid address to latch enable setup time (in multiplexed mode) 5 ns t5 invalid wr to address hold time (in non-multiplexed mode) 2 ns t6 valid data to inactive wr setup time 5 ns t7 inactive wr to data hold time 10 ns t8 active cs to inactive rdy delay time 6 12 ns t9 active wr to active rdy delay time 30 85 ns t10 inactive wr to inactive rdy delay time 10 15 ns t11 invalid cs to rdy high-z delay time 6 12 ns t12 address latch enable pulse width (in multiplexed mode) 10 ns t13 inactive ale to wr setup time (in multiplexed mode) 0 ns t14 inactive ale to address hold time (in multiplexed mode) 5 ns t15 address setup time to inactive wr time (in non-multiplexed mode) 5 ns note: 1. the t1 can be 15ns when rdy signal is not used. rdy d[7:0] a[7:0] ale(=1) wr cs t1 t5 t8 t9 t10 t11 address write data t15 6527 drw19 t2 t3 6 t 7 t rdy ad[7:0] ale wr cs t1 t2 t9 t13 write data address 6527 drw20 t3 t12 t4 t14 t6 t7 t8 t10 t11
46 industrial temperature ranges octal t1/e1 short haul analog front end figure 20. non-multiplexed motorola mode read timing symbol parameter min typ max unit comments t1 active ds pulse width 90 ns note 1 t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 0 ns t5 inactive ds to r/ w hold time 0.5 ns t6 valid address to active ds setup time (in non-multiplexed mode) valid address to as setup time (in multiplexed mode) 5 ns t7 active ds to address hold time (in non-multiplexed mode) active as to address hold time (in multiplexed mode) 10 ns t8 active ds to data valid delay time (in non-multiplexed mode) active as to data valid delay time (in multiplexed mode) 20 35 ns t9 active ds to data output enabletime 7.5 15 ns t10 inactive ds to data high-z delay time 7.5 15 ns t11 active ds to active ack delay time 30 85 ns t12 inactive ds to inactive ack delay time 10 15 ns t13 inactive ds to invalid int delay time 20 ns t14 active as to active ds setup time (in multiplexed mode) 5 ns note: 1. the t1 is determined by the start time of the valid data when the ack signal is not used. motorola mode read timing characteristics int ack d[7:0] a[7:0] ale(=1) ds cs t1 address data out r/ w t2 t3 t4 6527 drw21 t5 t6 t 7 t8 t10 t9 t12 t11 t13
47 industrial temperature ranges octal t1/e1 short haul analog front end int ack ad[7:0] as ds cs data out address r/ t1 t2 t3 t4 t5 t6 t12 t14 6527 drw22 w t8 t9 t7 t10 t11 t13 figure 21. multiplexed motorola mode read timing
48 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter min typ max unit comments t1 active ds pulse width 90 ns note 1 t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 10 ns t5 inactive ds to r/ w hold time 0 ns t6 valid address to active ds setup time (in non-multiplexed mode) valid address to as setup time (in multiplexed mode) 10 ns t7 valid ds to address hold time (in non-multiplexed mode) valid as to address hold time (in multiplexed mode) 10 ns t8 valid ds to inactive ds setup time 5 ns t9 inactive ds to data holdtime 10 ns t10 active ds to active ack delay time 30 85 ns t11 inactive ds to inactive ack delay time 10 15 ns t12 active as to active ds (in multiplexed mode) 0 ns t13 inactive ds to inactive as hold time (in multiplexed mode) 15 ns note: 1. the t1 can be 15ns when the ack signal is not used. motorola mode write timing characteristics ack d[7:0] a[7:0] ale(=1) ds cs t1 address write data r/ w t2 t3 t8 t10 6527 drw23 t4 t5 t6 t7 t9 t11 figure 21. non-multiplexed motorola mode write timing
49 industrial temperature ranges octal t1/e1 short haul analog front end ack ad[7:0] as ds cs write data address r/ w t1 t3 t5 t9 t10 t12 6527 drw24 t2 t4 t13 t6 t7 t8 t11 figure 23. multiplexed motorola mode write timing
50 industrial temperature ranges octal t1/e1 short haul analog front end symbol parameter min typ max unit comments t1 sclk high time 25 ns t2 sclk low time 25 ns t3 active cs to sclk setup time 10 ns t4 last sclk hold time to inactive cs time 50 ns t5 cs idle time 50 ns t6 sdi to sclk setup time 5 ns t7 sclk to sdi hold time 5 ns t8 rise/fall time (any pin) 100 ns t9 sclk rise and fall time 50 ns t10 sclk to sdo valid delay time 100 ns t11 sclk falling edges to sdo high-z hold time (clke = 0) 100 ns cs rising edges to sdo high-z hold time (clkd = 1) serial host interface timing characteristics msb lsb lsb cs sclk sdi t3 t4 t6 t7 6527 drw25 t1 t2 t5 t7 control byte data byte figure 24. serial interface writing timing 12345678910111213141516 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 6527 drw26 figure 25. serial interface read timing with clke = 0 12345678910111213141516 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 6527 drw27 figure 26. serial interface read timing with clke = 1
51 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1552 santa clara, ca 95054 fax: 408-492-8694 email: telecomhelp@idt.com www.idt.com ordering information idt xxxxxxx xx x device type blank process/ temperature range bb 82v2048 industrial (-40 to +85 ) plastic ball grid array (pbga, bb160) t1/e1 analog front end da thin quad flatpack (tqfp, da144) 6527 drw28 l c c

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